000-086 exam Dumps Source : System x high Performance Servers(R) Technical back V4
Test Code : 000-086
Test appellation : System x high Performance Servers(R) Technical back V4
Vendor appellation : IBM
: 43 actual Questions
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computer studying algorithms hold better through leaps and bounds in concomitant years. State-of-the-artwork methods like fb’s, as an instance, can educate image classification algorithms in an hour with out sacrificing accuracy. however a lot of them are educated on excessive-end machines with powerful GPUs, and as the cyber web of issues (IoT) industry moves towards aspect computing, there’s transforming into exact for low-energy synthetic intelligence (AI) fashions with low overhead.
Promising analysis out of IBM lays the groundwork for a lot greater efficient algorithms. on the 2018 convention on computer imaginative and prescient and pattern awareness in Salt Lake metropolis, Utah this week, analysis scientists from the company are offering two papers that deal with graphic classification.BlockDrop
the primary, titled “BlockDrop: Dynamic Interference Paths in Residual Networks,” builds on Microsoft’s drudgery on residual networks that became published in 2015. Residual networks (ResNets for brief) interject identification connections between the layers in the neural community, permitting them to learn incremental, or residual, representations in the course of practicing.
IBM takes this concept one step additional. Scientists brought a lightweight secondary neural community — mentioned within the paper as a “coverage network” — that dynamically dropped residual blocks in a pre-knowledgeable ResNet. To live certain the efficiency advantageous properties didn’t Come at the can saturate of precision, the coverage network turned into educated to create utilize of a minimal number of blocks and to reserve focus accuracy.
“commonly speakme, if you add more layers to a model, that you can enhance its accuracy, however you raise the computational charge,” IBM analysis manager Rogerio Feris instructed VentureBeat in a telephone interview. “One challenge with most present fashions these days is that you hold one-size-fits-all networks where the equal computation is applied to every bit of photos. [Our] device allocates supplies greater effectively and [can] accurately establish a picture.”
BlockDrop accelerated photograph classification by 20 percent on ordinary, and by means of as plenty as 36 p.c in certain cases, every bit of while maintaining seventy six.four percent accuracy — the equal as the scan’s control.improving stereo vision
The 2nd paper, “A Low energy, high Throughput, plenary event-primarily based Stereo equipment,” tackled one more rigor in photograph processing: stereo vision.
As IBM researcher Alexander Andreopoulos explained, human eyes are centimeters apart from each and every other and notice the realm from a bit of diverse views. The mind’s visible cortex seamlessly merges pictures from both eyes into one, allowing us to perceive depth, however two-digital camera robotics programs hold a more challenging time reconciling the disparity.
“within the case of laptop vision, camera lenses hold abnormalities, and this results in noise and complicates the problem,” Andreopoulos talked about.
The researcher’s solution: a device working on IBM’s TrueNorth neuromorphic chips, which hold a enormously parallelized structure optimized for laptop getting to know fashions. the utilize of a cluster of 9 processors, a pair of event-primarily based cameras (cameras that simplest snap an image once they notice action), and a desktop that disbursed computations to the aforementioned chips, the algorithms captured and processed four hundred (as much as a highest of 2,000) disparity maps per 2nd.
using event-based cameras greatly reduce down on bandwidth and energy usage, Andreopoulos defined. “Stereo algorithms hold been round for over 30 years, but most of these systems … utilize an vigorous manner to sensing the realm. Ours uses a passive strategy.”
photo credit: IBM
normal, the system validated a 200 times progress in terms of vigour per pixel per disparity map compared to state-of-the-artwork methods with exorbitant framerate cameras.
The consequences grasp vow for robotics techniques that depend on low-power, low-latency depth tips to navigate the world, Andreopoulos observed. “[I imagine] it getting used in accomplice robots for the elderly … [that] present some variety of mobility guidance.”
For now, AI techniques are commonly desktop learning-primarily based and “slim” – efficient as they are by nowadays’s standards, they’re constrained to performing a number of, narrowly-defined tasks. AI of the next decade will leverage the enhanced energy of abysmal gaining scholarship of and swirl into broader, solving a stronger array of extra advanced problems. moreover, the typical-aim applied sciences used these days for AI deployments will live replaced with the aid of a expertise stack that’s AI-specific and exponentially quicker – and it’s going to recall a lot of money.IBM’s Mukesh Khare
in search of to recall headquarters stage in AI’s unfolding, IBM – in combination with long island condition and several technology heavies – is investing $2 billion within the IBM research AI Hardware center, focused on setting up next technology AI silicon, networking and manufacturing in an exertion to, IBM noted, bring 1,000x AI efficiency effectivity progress over the subsequent decade.
“today, AI’s ever-increasing sophistication is pushing the boundaries of the trade’s existing hardware methods as clients learn more methods to involve various sources of statistics from the area, cyber web of issues, and greater,” stated Mukesh Khare, VP, IBM analysis Semiconductor and AI Hardware community, in a blog asserting the challenge. “…nowadays’s systems hold achieved more suitable AI performance by way of infusing desktop-getting to know capabilities with excessive-bandwidth CPUs and GPUs, really expert AI accelerators and high-performance networking device. To reserve this trajectory, recent pondering is needed to accelerate AI performance scaling to hale to ever-increasing AI workload complexities.”IBM roadmap for 1,000x improvement in AI compute performance efficiency.
IBM spoke of the headquarters may live the nucleus of a recent ecosystem of research and commercial companions participating with IBM researchers. partners announced these days involve Samsung for manufacturing and analysis, Mellanox technologies for prime-performance interconnect device, Synopsys for utility platforms, emulation and prototyping, and IP for constructing excessive-performance silicon chips, and semiconductor gadget companies utilized substances and Tokyo Electron.
Hosted at SUNY Polytechnic Institute, Albany, ny, in collaboration with neighboring Rensselaer Polytechnic Institute headquarters for Computational innovations, IBM referred to the enterprise and its partners will “enhance a compass of technologies from chip degree devices, substances, and architecture, to the utility assisting AI workloads.”
big Blue celebrated research on the middle will focus on overcoming present computing device-studying barriers via tactics that consist of approximate computing via Digital AI Cores and in-memory computing via Analog AI Cores. These applied sciences will provide the thousand-fold increases in performance effectivity required for plenary awareness of abysmal researching AI, in accordance with IBM.
“Our analog AI cores are a piece of an in-memory computing strategy in efficiency effectivity which improves through suppressing the so-referred to as Von Neuman bottleneck by means of putting off statistics switch to and from reminiscence,” referred to IBM. “Deep neural networks are mapped to analog retreat aspect arrays and recent non-unstable cloth characteristics are toggled to store network parameters in the pushover points.”
“A key district of research and construction will live techniques that meet the demands of abysmal gaining scholarship of inference and training techniques,” Khare referred to. “Such techniques present giant accuracy improvements over greater typical machine discovering for unstructured statistics. these fierce processing demands will develop exponentially as algorithms become more complicated so as to deliver AI programs with elevated cognitive potential.”
Khare observed the analysis headquarters will host R&D, emulation, prototyping, checking out and simulation activities for brand spanking recent AI cores in particular designed for practicing and deploying superior AI models, together with a test mattress in which contributors can pomp improvements in real-world applications. really advantageous wafer processing for the core can live accomplished in Albany with some usher at IBM’s Thomas J. Watson research middle in Yorktown Heights, the gigantic apple.
In September 2018, IBM announced a brand recent product, IBM Db2 AI for z/OS. This synthetic intelligence engine displays records access patterns from executing SQL statements, uses computing device researching algorithms to select most dependable patterns and passes this tips to the Db2 query optimizer to live used through subsequent statements.machine discovering on the IBM z Platform
In may additionally of 2018, IBM introduced version 1.2 of its computing device studying for z/OS (MLz) product. here's a hybrid zServer and cloud application suite that ingests efficiency data, analyzes and builds fashions that symbolize the health status of a considerable number of indications, displays them over time and gives real-time scoring capabilities.
a pair of elements of this product offering are geared toward supporting a neighborhood of mannequin builders and managers. as an example:
This machine getting to know suite changed into at the genesis geared toward zServer-based mostly analytics purposes. some of the first obvious decisions changed into zSystem performance monitoring and tuning. system administration Facility (SMF) statistics which are immediately generated by using the operating gadget supply the uncooked information for system resource consumption corresponding to valuable processor utilization, I/O processing, memory paging and so on. IBM MLz can collect and rescue these statistics over time, and construct and school models of system behavior, rating those behaviors, establish patterns now not easily foreseen via humans, enlarge key performance symptoms (KPIs) and then feed the mannequin consequences back into the system to move outfit configuration changes that can enlarge efficiency.
The subsequent step became to implement this suite to investigate Db2 performance facts. One answer, known as the IBM Db2 IT Operational Analytics (Db2 ITOA) retort template, applies the computer discovering know-how to Db2 operational information to profit an understanding of Db2 subsystem fitness. it will probably dynamically build baselines for key performance indicators, give a dashboard of those KPIs and give operational personnel true-time perception into Db2 operations.
whereas conventional Db2 subsystem performance is an Important component in habitual software health and efficiency, IBM estimates that the DBA back group of workers spends 25% or greater of its time, " ... fighting access path problems which cause efficiency degradation and repair impact.". (See Reference 1).AI involves Db2
agree with the plight of modern DBAs in a Db2 atmosphere. In state-of-the-art IT world they hold to back one or greater massive facts applications, cloud software and database capabilities, application setting up and configuration, Db2 subsystem and application performance tuning, database definition and administration, disaster recovery planning, and more. query tuning has been in being on account that the origins of the database, and DBAs are constantly tasked with this as smartly.
The heart of query direction evaluation in Db2 is the Optimizer. It accepts SQL statements from applications, verifies authority to access the statistics, experiences the places of the objects to live accessed and develops an inventory of candidate data entry paths. These access paths can encompass indexes, desk scans, a lot of table live piece of methods and others. within the data warehouse and massive facts environments there are always further decisions available. One of those is the being of abstract tables (sometimes called materialized query tables) that involve pre-summarized or aggregated facts, therefore permitting Db2 to steer lucid of re-aggregation processing. another option is the starjoin access direction, benchmark in the records warehouse, where the order of table joins is changed for performance factors.
The Optimizer then reports the candidate access paths and chooses the entry course, "with the lowest cost." saturate in this context potential a weighted summation of useful resource usage including CPU, I/O, reminiscence and different components. finally, the Optimizer takes the bottom can saturate entry route, shops it in memory (and, optionally, within the Db2 listing) and begins access direction execution.
big statistics and information warehouse operations now consist of utility suites that permit the company analyst to create utilize of a graphical interface to build and maneuver a miniature data model of the information they exigency to analyze. The packages then generate SQL statements in keeping with the clients’ requests.
The rigor for the DBA
so as to carry out first rate analytics for your diverse data stores you exigency a fine knowing of the data necessities, an figuring out of the analytical features and algorithms obtainable and a excessive-efficiency data infrastructure. regrettably, the number and site of information sources is increasing (each in measurement and in geography), facts sizes are growing to be, and purposes continue to proliferate in number and complexity. How should IT managers back this atmosphere, in particular with essentially the most experienced and develope staff nearing retirement?
take into account also that a great a piece of decreasing the total can saturate of possession of these techniques is to win Db2 functions to Run faster and more efficiently. This usually translates into using fewer CPU cycles, doing fewer I/Os and transporting less records throughout the network. when you consider that it's regularly complicated to even establish which functions might capitalize from performance tuning, one approach is to automate the detection and correction of tuning concerns. here's the plot machine researching and artificial intelligence can live used to remarkable impact.Db2 12 for z/OS and artificial Intelligence
Db2 edition 12 on z/OS makes utilize of the computing device learning amenities mentioned above to collect and rescue SQL question textual content and entry route particulars, in addition to specific performance-related conventional tips reminiscent of CPU time used, elapsed times and outcome set sizes. This offering, described as Db2 AI for z/OS, analyzes and retailers the records in machine discovering models, with the model evaluation effects then being scored and made attainable to the Db2 Optimizer. The subsequent time a scored SQL remark is encountered, the Optimizer can then utilize the mannequin scoring records as enter to its access direction alternative algorithm.
The result should live a reduction in CPU consumption as the Optimizer makes utilize of model scoring enter to opt for stronger entry paths. This then lowers CPU prices and speeds utility response times. a gigantic expertise is that the usage of AI software doesn't require the DBA to hold statistics science talents or abysmal insights into query tuning methodologies. The Optimizer now chooses the benchmark access paths based now not best on SQL question syntax and records distribution facts but on modelled and scored conventional efficiency.
This may also live specially essential in case you reserve information in varied areas. as an example, many analytical queries towards massive facts require concurrent entry to certain information warehouse tables. These tables are generally known as dimension tables, and that they comprise the records elements constantly used to control subsetting and aggregation. as an instance, in a retail ambiance believe a table known as StoreLocation that enumerates every rescue and its plot code. Queries towards shop income facts may additionally exigency to combination or summarize income by way of vicinity; therefore, the StoreLocation table might live used by way of some massive statistics queries. in this ambiance it's commonplace to recall the dimension tables and copy them always to the gigantic data application. within the IBM world this district is the IBM Db2 Analytics Accelerator (IDAA).
Now consider about SQL queries from both operational functions, data warehouse clients and massive data industry analysts. From Db2's standpoint, every bit of these queries are equal, and are forwarded to the Optimizer. youngsters, in the case of operational queries and warehouse queries they should surely live directed to entry the StoreLocation table in the warehouse. then again, the query from the company analyst in opposition t gigantic statistics tables should noiseless likely entry the reproduction of the desk there. This outcomes in a proliferations of skills entry paths, and greater drudgery for the Optimizer. fortunately, Db2 AI for z/OS can supply the Optimizer the suggestions it needs to create sensible entry direction choices.how it Works
The sequence of movements in Db2 AI for z/OS (See Reference 2) is often here:
There are also numerous person interfaces that supply the administrator visibility to the repute of the accumulated SQL observation efficiency information and model scoring.abstract
IBM's desktop discovering for zOS (MLz) offering is getting used to fantastic sequel in Db2 edition 12 to enhance the efficiency of analytical queries as well as operational queries and their associated functions. This requires administration attention, as you should investigate that your company is ready to devour these ML and AI conclusions. How will you measure the prices and advantages of using desktop gaining scholarship of? Which IT assist group of workers ought to live tasked to reviewing the influence of model scoring, and perhaps approving (or overriding) the consequences? How will you review and justify the assumptions that the software makes about entry direction choices?
In different words, how well did you know your information, its distribution, its integrity and your latest and proposed access paths? this will check the plot the DBAs expend their time in aiding analytics and operational software efficiency.
# # #
John Campbell, IBM Db2 unusual EngineerFrom "IBM Db2 AI for z/OS: raise IBM Db2 application efficiency with desktop researching"https://www.worldofdb2.com/activities/ibm-db2-ai-for-z-os-boost-ibm-db2-utility-efficiency-with-ma
Db2 AI for z/OShttps://www.ibm.com/support/knowledgecenter/en/SSGKMA_1.1.0/src/ai/ai_home.html
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X-Engine is a recent generation storage engine developed by Alibaba Database Department and is the basis of the distributed database X-DB. To achieve 10 times the performance of MySQL and 1/10 the storage cost, X-DB combines software with hardware to create plenary utilize of the most cutting-edge technical advantages in both software and hardware fields.
FPGA acceleration is their first attempt in the custom computing field. At present, the FPGA-accelerated X-DB has been matter to small-scale online grayscale release. FPGA will assist X-DB in the 6.18 and Double 11 shopping carnivals this year and will meet Alibaba's industry departments' high database performance requirements.Overview of Alibaba's X-Engine
Owning the world's largest online transaction website, Alibaba's OLTP (online transaction processing) database system needs to answer high-throughput service requirements. According to their statistics, several billion records win written into their OLTP database system on a daily basis. During the 2017 Double 11 (Singles' Day) shopping carnival, the system's peak throughput reached 10 million TPS (transactions per second). Alibaba's industry database systems mainly hold the following characteristics:
To meet Alibaba's stringent requirements on performance and cost, they hold designed a recent storage engine; it is called X-Engine. They hold used many cutting edge database technologies in X-Engine; these involve highly-efficient memory index structures, asynchronous write assembly-line processing mechanism, and optimistic concurrency control for in-memory databases.
To achieve the best write performance and facilitate the separation of glacial and burning data for tiered storage, X-Engine has borrowed the design of LSM-Tree. X-Engine maintains multiple memtables in its memory. It appends every bit of newly written data to these memtables, rather than directly replacing existing records. As the data storage is relatively large, it is impossible to store every bit of data in memory.
When data in memory reaches a specified volume, they flush it to the persistent storage to shape an SSTable. To reduce latency in read operations, X-Engine regularly schedules compaction tasks to compact SSTables in the persistent storage. X-Engine merges key-value pairs in multiple SSTables by keeping only the latest version of key-value pairs if multiple versions exist (all key-value pair versions currently referenced by transactions will also live kept).
Based on the characteristics of data access, X-Engine applies tiered storage to persistent data, where they store vigorous data in relatively high data layers, and merge less vigorous data (seldom accessed) with base-layer data and store it in the base-layer. It compresses base-layer data at a high compression rate and migrates it to storage media featuring great capacity but the relatively low cost (such as SATA HDDs) to achieve the goal of storing a great quantity of data at a relatively low cost.
In this case, tiered storage creates a recent problem: the system must frequently compact data, and the larger number of data writes requires more frequent compaction processes. Compaction is a compare and merge process which requires high consumption of CPU and storage I/O. In high-throughput write cases, a great number of compaction operations will occupy a great number of system resources. This can surely cause the performance of the entire system to drop tremendously thus leading to a huge impact on the application system.
The completely recent X-Engine has extraordinary multi-core expansion capability to achieve very high performance. Its front-end transaction solitary can almost completely consume every bit of CPU resources, and it has a much higher resource using efficiency than InnoDB. They hold shown the comparison between the two in the following figure:
At such a performance level, the system does not hold any other resources for compaction operations; otherwise, performance levels will drop.
Based on their testing results, in DbBench benchmark's write-only scenario, the system periodically suffers from performance jitter. When a compaction assignment occurs, the system performance drops by more than 40%, and when the compaction assignment ends, the system performance returns to normal. They hold shown this deportment in the following figure:
However, if they carry out not conduct compaction promptly, the accumulation of multi-version data can seriously move the read operations.
To decipher the performance jitter caused by compaction, academic experts hold build forward many structures such as VT-tree, bLSM, PE, PCP, and dCompaction. Although these algorithms can optimize the compaction performance across multiple aspects, they cannot reduce consumption of CPU resources by compaction. Based on material research statistics, when using SSD storage devices, the computing operations of compaction in the system consumes approximately 60% of computing resources. Therefore, no matter what optimizations they implement for compaction in the software layer, for every bit of LSM tree-based storage engines, performance jitter caused by compaction is always an Achilles' heel.
Fortunately, special hardware opens a recent door for solving performance jitter caused by compaction. In fact, it has become a trend to utilize special hardware in solving traditional databases' performance bottlenecks. They hold already offloaded database operations such as Select and Where to FPGA, and more involved operations such as Group By are under research. However, the current FPGA acceleration solutions hold a pair of drawbacks:
To ease the impact of compaction on X-Engine's system performance, they hold used an asynchronous hardware device FPGA, rather than the CPU to complete the compaction operation. This approach is crucial for a storage engine that satisfies stringent service requirements by maintaining the overall system performance at a high-level and avoiding performance jitters. Here are the major design features:
X-Engine's storage structure contains one or multiple memory buffer areas (memtable), and multilayer persistent storage L0, L1... Each layer contains multiple SSTables.
When memtable is full, it turns into an immutable memtable and then flushes to an SSTable to L0. Each SSTable contains multiple data blocks and one index shroud to index the data block. When it reaches the maximum number of L0 files, it triggers the merge of SSTables that hold the overlapped key ranges; this process is called compaction. Likewise, when they attain the maximum number of SSTables at a layer, it merges with lower layer data. In this way, glacial data constantly flows downward while burning data remains at a relatively higher layer.
We can specify a compass of key-value pairs that merge during a compaction process and this compass may hold multiple data blocks. Generally, a compaction process involves merging data blocks between two adjacent layers. However, they exigency to pay special attention to compaction tasks between L0 and L1. This is because as SSTables in L0 directly flushes from the memory, keys of SSTables in this layer may win overlapped. Therefore, a compaction assignment between L0 and L1 may involve merging multiple data blocks.
For read operations, X-Engine needs to search for the required data from every bit of memtables. If it fails to find the data in memtables, it searches in the persistence storage, from higher to lower layers. As a result, timely compaction operations not only curtail the read path but also rescue the storage space. However, this manner uses a lot of system computing resources and causes performance jitter. This is an imperative problem that X-Engine must solve.FPGA Accelerated Database
From the perspective of the existing FPGA accelerated databases' status quo, they can divide FPGA accelerated database architectures into two types; the bump-in-the-wire design and the hybrid design. In the early stage, because of the FPGA card's insufficient memory resources, the former character of architecture is relatively popular. In this architecture, they plot FPGA on the storage data path and utilize the host as a filter. The odds is that it requires zero data replication, while the drawback is that the acceleration operation must live a piece of the streamlined process, therefore making it not resilient enough in terms of the design method.
The latter architecture design uses FPGA as a coprocessor, where they hold connected FPGA to host via PCIe and utilize the DMA manner for data transmission. As long as the offloading computation is intensive enough, data transmission costs are acceptable. The hybrid architecture design allows more resilient offloading methods. For involved operations such as compaction, data transmission between FPGA and host is necessary. Therefore, they hold used the hybrid architecture design for hardware acceleration in their X-Engine.
In traditional LSM-tree-based storage engines, CPU is answerable for handling unpretentious user requests, as well as the scheduling and execution of compaction tasks. In other words, CPU is both the producer and consumer of compaction tasks. However, in a CPU-FPGA hybrid storage engine, CPU is only answerable for producing and scheduling compaction tasks. In this method, they exigency to offload the execution of compaction tasks to the special hardware (FPGA).
For X-Engine, handling of unpretentious user requests is similar to that of LSM-tree-based storage engines:
When L0 reaches the maximum number of SSTables, compaction gets triggered. They can divide offloading of a compaction assignment into the following steps:
Compaction Units (CU) are the basic unit for FPGA to execute compaction tasks. An FPGA card can plot multiple CUs, and each CU is composed of the following modules:
1. Decoder: In X-Engine, they store a KV in the data shroud after compression and encoding. The primary role of the Decoder module is to decode KV pairs. Each CU contains 4 Decoders, and a CU back a compression assignment of a maximum of 4 KV pairs. They exigency to split the compression tasks that require compression of more than 4 KV by the CPU. Based on their assessment, most compression tasks involve less than 4 KV pairs. They hold placed 4 Decoders based on their considerations of performance and hardware resources. Comparing the configuration with 2 Decoders, we've increased 100% hardware consumption but obtained 300% performance improvement.
A compaction process contains three key steps: decoding, merging, and encoding. The most significant challenge for designing a proper compaction pipeline is that the execution time for each step varies significantly. For example, because of parallel processing, the throughput of the decoder module is much higher than the encoder module. Therefore, they must suspend some fleet modules to wait for downstream modules noiseless in the pipeline. To match the throughput differences in each of the pipeline's modules, they hold designed a Controller module to coordinate different steps in the pipeline. An additional capitalize of this design is that it decouples each module in the pipeline and enables more resilient progress and maintenance during engineering implementation.
When integrating FPGA compaction into X-Engine they hope to hold independent CU throughput performance; the baseline of the experiment is the CPU.
Single-core compaction thread (Intel(R) Xeon(R) E5-2682 v4 CPU with 2.5 GHz)
We can draw the following three conclusions from the experiment:
Because a link request in FPGA is completed in milliseconds, using the traditional synchronous scheduling manner will cause high thread switching costs. Based on FPGA's characteristics, they hold redesigned an asynchronous scheduling compaction method, where:
Asynchronous scheduling significantly reduces the thread-switching cost of CPU.
Fault Tolerance Mechanism Design
For FPGA compaction, the following three reasons can lead to the failure of compaction task:
To ensure the data is correct, the CPU will conduct computation again on every bit of failed tasks. As they mentioned earlier in the frailty tolerance mechanism, they hold addressed a tiny piece of compaction tasks that exceed the limits and hold avoided the risk of FPGA internal errors.
Experiment Results Lab environment
We compared the performance of two storage engines:
We hold included testing for InnoDB in this experiment (buffer size = 80 GB)
In this article, the X-Engine storage engine accelerated by FPGA brings 50% performance improvement for the KV interface, and 40% performance improvement for the SQL interface. With the dwindle in the read/write ratio, FPGA's acceleration sequel becomes more obvious, thus sense that FPGA compaction acceleration is suitable for write-intensive workloads. This is consistent with the intention of the LSM-tree design. Also, they hold avoided FPGA's internal defects by designing a frailty tolerance mechanism, and we've finally created a high-availability CPU-FPGA hybrid storage engine that meets Alibaba's actual service requirements.
It is the first actual project that uses a heterogeneous computing device introduced by X-DB to accelerate core database functions. Based on their experiences, FPGA can completely meet the computing demands raised by X-Engine's compaction tasks. At the same time, they hold been researching to schedule more suitable computing tasks to FPGA for execution, such as compression, BloomFilter generation, and SQL associate operators. At present, the R&D for the compression role is completed, and it will live built into a set of IP together with Compaction to fulfill data compaction and compression operations simultaneously.
X-DB FPGA-Compaction hardware acceleration is an R&D project completed by three parties; these parties are respectively the Alibaba Database Department database kernel team, the Alibaba Server R&D Department custom computing team, and Zhejiang University. Xilinx's technical team has also made remarkable contributions to the success of this project. They hereby extend their gratitude to them. They will post X-DB online for public beta this year. You will then live able to suffer the significant performance improvement with FPGA acceleration to X-DB.
When the time comes to buy server hardware, there are a lot of factors to consider, such as the number of processors, the available memory and the total storage capacity. Buyers should closely evaluate eight Important features when comparing the servers available from the leading vendors.
These eight features cover the basic components to quest for to buy server hardware, but they don't picture every bit of the features that buyers should consider. Decision-makers at every organization must determine exactly what they exigency to back their existing and future workloads, keeping in intellect the differences between rack, blade and mainframe computers.
Companies should view these eight features as the starting point to identify their requirements and evaluate the available products and should expand their research as necessary to ensure they're addressing every concern.Processors
One of the most Important components to consider when buying server hardware is the processor that carries out the data computations. also referred to the central processing unit (CPU), the processor does every bit of the cumbersome lifting when it comes to running programs and sifting through data. Most servers Run multiple processors, usually with one per socket. However, a processor can also live made up of multiple cores to back multiprocessing capabilities.
Multiple cores usually translate to better performance, but the number of cores is not the only factor to consider. Buyers should also consider the processor precipitate -- CPU clock precipitate -- and available cache, as well as the total number of sockets, as these can vary significantly from one processor to the next.
For example, the NEC Express5800/D120h blade server supports up to two processors from the Intel Xeon Scalable product family. One of the most robust of these processors offers 26 cores, 35.75 MB of cache and a 2.0 GHz clock speed.
Compare that to the Dell PowerEdge M830 blade server, which uses Xeon E5-4600 v4 processors. The most robust of these offers 22 cores, 55 MB of cache and a 2.20 GHz clock speed. The Dell server also supports up to four processors rather than two.Memory
Adequate server memory is essential to a high-performing system, and the more memory that is available, the better the workloads are likely to perform. However, other factors can also contribute to performance, such as the memory's precipitate and quality. Most server memory is made up of dual in-line memory module integrated circuit boards with some character of random-access memory.
Companies should view these eight features as the starting point to identify their requirements and evaluate the available products and should expand their research as necessary to ensure they're addressing every concern.
Server memory might also involve fault-tolerant capabilities or other features that enhance reliability. One of the most common capabilities is error-correcting code (ECC), a manner to detect and reform common single-bit errors. When evaluating server hardware memory, you should quest at the entire offering, keeping in intellect the types of workloads and applications you run.
For example, Fujitsu's mainframe computers in the BS2000 SE string back up to 1.5 TB of memory. However, IBM's ZR1 mainframe, which is piece of the z14 family, supports up to 8 TB of memory. The ZR1 also provides up to 8 TB of available redundant array of independent memory to better transaction response times, a pre-emptive dynamic RAM feature to seclude and retrieve from failures quickly, and ECC technologies to detect and reform bit errors.Storage
Servers vary greatly in the amount and types of internal storage that they support, in piece because workflows and applications also vary. For example, a server hosting a relational database management system will hold different requirements than one hosting a web application. In addition, the utilize of external storage, such as storage district networks (SANs), can also impact internal storage requirements.
When you buy server hardware, live confident to evaluate each prospective server to ensure it can meet your storage needs. Today, most servers back both solid-state drives (SSDs) and arduous disk drives (HDDs). But buyers should certainly verify this support, as well as the server's supported drive technologies, such as Serial-Attached SCSI (SAS), Serial Advanced Technology Attachment (SATA) or non-volatile memory express (NVMe). Other considerations should involve drive speeds, capacities, endurance and back for redundant array of independent disks (RAID).
For example, Oracle's X7-2 rack server can back up to eight 2.5-inch HDDs or SSDs, either SAS or NVMe, and multiple RAID configurations. Compare that to the Inspur TS860G3 rack server, which can handle up to 16 drives, either SSDs or HDDs, and back both SAS and SATA. However, the Inspur server does not back NVMe, which means the SSDs might not fulfill as well.Connectivity
A server's skill to connect to networks, peripherals, storage and other components is essential to its effectiveness within the data center. The server needs the necessary connectors and drivers to ensure that it can properly communicate with other entities and process various workloads. Buyers exigency to determine exactly what character of connectivity is necessary and, from there, examine the server's specs to verify whether it will meet those requirements.
Servers vary widely in this regard, so buyers should quest for specifics such as the number and precipitate of the Ethernet connectors, the number and character of USB ports, the availability of management interfaces, the types of protocols available, back for SANs and other storage systems, as well as whatever other components are necessary to facilitate connectivity.
Acer's rack server Altos R380 F3 is a advantageous example of what connectivity features to quest for when you buy server hardware. It includes two Ethernet ports, either 1 GB or 10 GB, an RJ-45 management port, three USB 3.0 ports, one USB 2.0 port, and a video port. In addition, the server offers up to seven Peripheral Component Interconnect Express (PCIe) 3.0 slots and one PCIe 1.0 slot.Hot swapping
Servers present burning swapping capabilities to varying degrees. burning swapping refers to the skill to supplant or add a component without needing to shut down the system.
The term burning plugging sometimes refers to burning swapping, although, in theory, burning plugging capabilities are limited to being able to add components but not supplant them without shutting down the system. Because of the confusion around these terms, it is best to verify how each vendor uses them.
One of the most common burning swappable components is the disk drive. For example, the Cisco UCS B480 M5 blade server supports burning swappable drives, as does the Huawei FusionServer CH242 V5 blade server and the Intel R2224WFQZS rack server.
With blade systems, the burning swapping capabilities are often within the chassis itself. One example is the chassis used for the Lenovo ThinkSystem SN850 blade server, which provides burning swapping capabilities for the fans and power supplies, in addition to the server's disk drives. However, these types of capabilities are not limited to blade servers. The Acer Altos R380 F3 system also supports burning swappable fans and power supplies even though it is a rack server.Redundancy
Redundancy is Important to ensure a server's continued operation in the event of a component failure. Most servers provide some flush of redundancy, often for the arduous drives, power supplies and fans. The Asus RS720-E9-RS12-E rack server, for example, offers redundant power supplies and the HPE ProLiant DL380 Gen10 rack server offers redundant fans.
As with its burning swapping capabilities, the redundancy available to blade servers is often located within the chassis. For instance, the chassis that back the Dell PowerEdge M830 blade server and Supermicro SBI-6129P-T3N blade server both provide redundant power supplies.
However, the Dell chassis also offers redundant cooling components, and the server itself provides redundant embedded hypervisors.Manageability
Admins must manage a server effectively to ensure its continued operation while delivering optimal performance. Most servers provide at least some management capabilities.
For example, many servers back the brilliant Platform Management Interface (IPMI), a specification developed by Dell, Hewlett Packard, Intel and NEC to monitor and manage server systems. Not surprisingly, the servers offered by these companies, such as the Dell PowerEdge M830, HPE ProLiant DL380 Gen10, Intel Server System R2224WFQZS and NEC Express5800/B120g-h, are IPMI-compliant.
But servers are certainly not limited to IPMI capabilities. For example, the Acer Altos R380 F3 rack server comes with the Acer Smart Server Manager; the Asus RS720-E9-RS12-E rack server comes with the ASUS Control Center; and the Cisco Unified Computing System (UCS) B480 M5 blade server comes with Cisco Intersight, Cisco UCS Manager, Cisco UCS Central Software, Cisco UCS Director and Cisco UCS Performance Manager.
Blade systems usually provide some character of module to manage the individual blades. For instance, Huawei's FusionServer CH242 V5 blade system includes the brilliant Baseboard Management System module to monitor the compute node's operating status and back remote management.
Not surprisingly, systems such as Fujitsu's BS2000 mainframes provide a variety of management capabilities. For example, each BS2000 system includes a management unit that works in conjunction with the SE Manager to present a centralized interface from which to administer the entire server environment. And IBM's ZR1 mainframe includes the IBM Hardware Management Console (HMC) 2.14, the IBM Dynamic Partition Manager and an optimized z/OS platform for IBM Open Data Analytics.Security
Another Important factor to consider is the server's security features. As with other features, servers can vary significantly in what they offer, with each vendor taking a different approach to securing their systems.
For example, the Lenovo ThinkSystem SN850 blade server provides an integrated Trusted Platform Module 2.0 chip to store the RSA encryption keys used for hardware authentication. The server also supports Secure Boot, Intel Execute Disable Bit (EDB) functionality and Intel Trusted Execution Technology.
Another example is the Oracle Server X7-2 rack server, which comes with the Oracle Integrated Lights Out Manager 4.x, a cloud-ready service processor for monitoring and managing system and chassis functions. On the other hand, the Huawei FusionServer CH242 V5 blade server supports the Advanced Encryption benchmark -- recent Instructions, as well as Intel's EDB feature and Trusted Execution Technology.
IBM's ZR1 mainframe is also strong when it comes to security. The server includes on-chip cryptographic coprocessors and the Central Processor Assist for Cryptographic role (CPACF), which includes the recent Crypto Express6S feature to enable pervasive encryption and back a secure cloud strategy. The CPACF is benchmark on every core. The platform also includes IBM Secure Service Containers to securely deploy container-based applications.
Higher density fan-out packages are poignant toward more involved structures with finer routing layers, every bit of of which requires more capable lithography outfit and other tools.
The latest high-density fan-out packages are migrating toward the 1µm line/space barrier and beyond, which is considered a milestone in the industry. At these captious dimensions (CDs), fan-outs will provide better performance, but there are several manufacturing and cost challenges to attain and crash the 1µm barrier. Moreover, at this point only a few customers require these high-end packages.
Nevertheless, fan-out packaging is gaining steam in high-volume markets. “Mobile continues to live one main growth driver for both low-density and high-density fan-out,” said John Hunt, senior director of engineering for ASE. “Automotive will start to pick up momentum, as they win fan-out qualified for grade 1 and 2. And server applications are seeing growth for the high-end market.”
A key piece of a fan-out is the redistribution layer (RDL). RDLs are the copper metal connection lines or routing layers that electrically connect one piece of the package to another. RDLs are measured by line and space, which advert to the width and pitch of a metal line.
Fig. 1: Redistribution layers. Source: Lam Research
From there, fan-out is split into two segments—low-density and high-density. Low-density fan-out consists of RDLs with greater than 8μm line/space (8-8μm). Used in servers and smartphones, high-density fan-out has multiple layers of RDLs in a package, with CDs at 8-8μm and below. Generally, 5-5µm is the mainstream high-density technology, with 1-1µm and below in the works.
“There is noiseless a wide compass of fan-out character of technologies in terms of how aggressive they are regarding the design rules. A lot of it is dominated by shape factor, what you want for performance, and what you can tolerate for cost,” said Warren Flack, vice president of worldwide lithography applications at Veeco. “Redistribution layers with smaller captious dimensions enable reducing the total number of redistribution process levels in a fan-out package. This in swirl reduces the total packaging cost and improves yield.”
Cost is a factor on several fronts. Not every bit of exigency high-density fan-out. Fan-out with aggressive CDs are relatively expensive and limited to high-end customers. The advantageous tidings is that there is a plethora of other and lower cost packaging options besides high-density fan-out.
Then, on another front, customers are pushing the packaging houses to reduce their manufacturing costs, especially for fan-out and other advanced packages. In fan-out, there are several process steps, including lithography, the know-how of patterning features on structures.
In packaging, there are several different lithography utensil types, such as aligners, direct imaging, laser ablation and steppers. Each technology is different with various capabilities. every bit of told, packaging houses will likely utilize different utensil types for fan-out.
What is fan-out?Fan-out packaging is a burning market. In fan-out, the dies are packaged while on a wafer. Fan-out doesn’t require an interposer, making it less expensive than 2.5D/3D.
There are three types of fan-out packages—chip-first/face-down; chip-first/face-up; and chip-last or RDL first.
In the chip-first/face-down flow, the chips are first processed on a wafer in the fab. The wafer is moved to a packaging house, where the chips are diced. Then, using a die attach system, the dies are placed on a temporary carrier.
An epoxy mold compound is molded over the dies and carrier, forming what’s called a reconstituted wafer. Then, the RDLs are formed within the round reconstituted wafer.
In a simple RDL flow, a copper seed layer is deposited on the substrate. A photoresist is applied on the structure and then patterned using a lithography tool. Finally, an electroplating system deposits the copper metallization within the package, forming the final RDLs.
The RDL CDs depend on the application. Many fan-out packages don’t require advanced RDLs. Packages at 5-5µm and above will remain the mainstream technologies for the foreseeable future. Then, at the high end, ASE is poignant toward RDLs at or near 1-1μm. Meanwhile, TSMC is developing fan-out at 0.8μm with 0.4μm in R&D. Eventually, high-end fan-out will back high-bandwidth memory (HBM).
“There are different approaches of doing fan-out. They notice a trend where the CDs are getting smaller and more challenging. Copper pillar pitch is also getting smaller,” said Y.C. Wong, common manager of Veeco’s Litho System Asia industry unit. “Typically, for mainstream, the RDLs are noiseless 5-5μm and above in production. They are seeing some tiny volume at 2-2μm or 3-3μm. 1-1μm is just engineering tape-out right now. every bit of of this will live driven when 5G takes off and when memory bandwidth exact becomes higher. That will drive more exact for 2-2μm and 3-3μm and below.”
Nonetheless, there are several challenges with every bit of fan-out. “The main challenge with fan-out is the warpage/wafer bow. In addition, die placing can also impact wafer flatness and stress on the dies. Then, die shift induces challenges for the lithography steps and alignments,” said Amandine Pizzagalli, an analyst at Yole Développement.
Cost is also key. Packages with aggressive CDs minister to live more expensive. On the flip side, packages with more relaxed CDs are less expensive. In either case, customers are cost sensitive when it comes to IC packaging. They want to reduce their packaging costs as much as possible. So, they want the packaging houses to drive down their manufacturing costs.
There is another side to the story. A packaging customer may want a fan-out product with aggressive RDLs. But the package must achieve a certain volume to justify the R&D. If the package can’t meet a volume target, it’s difficult to win a return. And so, there may not live an incentive to pushover to a package with smaller RDLs.
Aligners to steppersTo live sure, lithography plays a key role in fan-out and other packaging types. It is also captious in the fab, where lithography outfit is used to pattern features at the nanoscale. Meanwhile, in packaging, lithography and other tools are used to process bumps, copper pillars, RDLs and through-silicon vias (TSVs). These structures are measured at the μm level.
In total, the lithography outfit market for packaging is expected to attain $141.6 million in 2019, up from $128.7 million in 2018, according to Yole Développement. Some 85% of every bit of recent outfit purchases involve steppers, followed by mask aligners with less than 15%, according to Pizzagalli.
Aligners and steppers plunge into a category called photolithography or optical lithography. For this, the process starts with a photomask. A designer designs an IC or a package, which is then translated into a file format. Then, a photomask is developed based on that format.
The photomask is a master template for a given design. After a mask is developed, it is shipped to the fab or packaging house. The mask is placed in a lithography tool. The utensil projects light through the mask, which patterns the images on a device.
For years, mask aligners were the mainstream lithography utensil for packaging. “Mask aligners drudgery by directing the projection of a full-area photomask to a substrate. Due to the fact that there is no reduction of projection optics, the mask has to live placed in close proximity to the wafers. Hence, the resolution is limited to about 3µm line/space for production applications,” said Thomas Uhrmann, director of industry progress at EV Group.
Today, mask aligners are used for packages, MEMS, and LEDs. “While line/space requirements below 3µm are tough to attain in production, mask aligners hold other benefits in advanced packaging. For example, mask aligners hold performance and cost advantages in the areas of bumping and thick resist exposure where high intensities and high exposure times are needed,” Uhrmann said.
For more advanced applications, though, the industry has migrated to a lithographic system called a stepper. Using advanced projection optics, steppers hold higher resolutions than aligners.
A stepper transfers the image of a feature from a mask onto a tiny portion of a wafer. The process is repeated until the wafer is processed. Canon, Rudolph, Veeco and others compete in the stepper market for packaging.
For many apps, packaging houses moved to steppers for several reasons. “When they started to quest at what the stepper could do, they could present some stagy improvements,” Veeco’s Flack said. “Decreasing CDs hold been a gigantic consideration in the eventual few years. It’s tightening the overlay to match the CDs. And now, there’s a much wider compass of substrates that you must live able to handle.”
Meanwhile, in the fab, chipmakers utilize 193nm wavelength lithography systems to print tiny features. In packaging, though, the feature sizes are larger, so packaging houses don’t require tools at these wavelengths. Instead, they utilize lithographic outfit at longer wavelengths, namely 436nm (g-line), 405nm (h-line) and 365nm (i-line).
In packaging, some steppers are i-line only, while others back more wavelengths. For example, Veeco sells what it calls a broadband stepper, which supports every bit of three wavelengths–436nm, 405nm and 365nm. These are produced by a broadband spectrum mercury light.
Fig. 2: Inside Veeco’s stepper. Source: Veeco
For more aggressive CDs, this stepper can live tuned to back an “i-line only” mode, enabling features down to 1-1μm. Additionally, the utensil can back a “ghi” mode, enabling features above 2-2μm.
Steppers are used to bear a compass of IC packages, including fan-out. In fan-out, lithography tools inspirit shape the RDLs.
These systems must also deal with die shift. As stated, when the dies are embedded in a reconstituted wafer, they minister to pushover during the flow, causing an unwanted sequel called die shift. This impacts the yield.
In response, the industry is developing lithography tools with better alignment techniques to compensate for die shift. “There are two ways you can address it. From a lithographic standpoint, you can reform it as much as you can. You can adjust the scales across the wafer. You can adjust the magnification. But that assumes everything shifts the same way. If the shifts are random, then it’s almost impossible to reform that way,” Veeco’s Flack said. “For higher desist applications, people will drudgery arduous to create confident the die doesn’t shift. That can live done by the technique of placing the die and aligning the die in some cases.”
Die shift remains an ongoing challenge in every bit of fan-out. Another challenge is to bear the RDLs. With itsy-bitsy or no trouble, the industry is making fan-out with RDLs at 5-5μm. Even 2-2μm is in production.
The challenges grow as fan-out moves to 1-1μm and beyond. The trick is to bear fine RDLs with advantageous yield.
The industry is capable of 1-1μm. For example, using an i-line only mode in a stepper, Veeco has demonstrated resolutions at 1-1μm. The stepper has a variable numerical aperture (NA) lens and 1X reticle.
There are some challenges. During the RDL process, the copper thickness must live maximized to lower the resistance of the metal lines, according to a recent paper from Veeco and Imec. So, the aspect ratio of the photoresist must live maximized. This, in turn, requires lithography tools with a great depth of focus to handle the height variations in fan-out, according to the paper.
Meanwhile, others present i-line only systems. For example, Canon’s latest i-line utensil features a 0.24 NA lens, enabling resolutions at ≤0.8μm.
“Leading-edge 1µm advanced packaging processes require the utilize of chemically amplified resists that are only sensitive to i-line wavelengths due to their photo acid generator properties. So it requires i-line exposure light to realize less than 1µm resolution,” said Doug Shelton, marketing manager at Canon. “Customers requesting wide-band exposure will live targeting scabrous pattern layers using develope DNQ resists that hold sensitivity to i-line and h-line resists, not g-line. For these less challenging applications, they can prepare a system with an option to allow wide-band i/h-line exposure to boost throughput for scabrous processes.”
So, it’s certainly feasible to shove the RDLs beyond 1µm using today’s technologies, but that remains unclear. It’s a matter for debate in the packaging industry. Regardless of the stepper type, though, there are several challenges in going beyond 1-1μm. The lithography tools are certainly capable, but there are other issues regarding the current RDL flow.
“When you win down below 1-1μm, you start to hold other issues that are not lithography related, which will restrict the precipitate of adoption,” Veeco’s Flack said. “As long as the seed layer is a tiny percentage of the width of the copper line, it works great. When you win down to less than 1μm, the seed layer is a significant percentage of the linewidth. As a result, you start to hold defer problems.”
Simply put, the traditional RDL process poses as a potential roadblock poignant beyond 1-1μm. “It will live a actual challenge for the industry with the transition at that point,” Flack said.
So the industry is looking at other process flows, namely dual damascene. For years, chipmakers hold used a damascene process to create the copper interconnects in chips in the backend-of-the-line (BEOL) in a wafer fab.
In dual damascene, the process steps are similar for both the BEOL and packaging. In packaging, an insulating layer is deposited on the device. Then, a trench is patterned and etched and the trench is filled with copper.
For packaging, the damascene flow works, and it’s feasible to shove the RDLs beyond 1-1μm. “It works great, but it’s just expensive. There’s a technical solution, but it may not live a cost-effective solution,” Flack said.
TSMC is exploring the damascene process, but it may live too costly for most. So the industry needs a cost-effective breakthrough in the arena.
Laser imaging, ablation and othersLaser direct imaging is another lithographic technique for packaging. Laser imaging is dote direct-write or maskless lithography. It directly writes features on a die without a mask, thereby reducing the cost in packaging.
Orbotech and Screen sell laser direct imaging systems. Deca Technologies also has developed a proprietary laser direct technology.
Laser imaging could decipher the die shift issues in fan-out. As stated, the first step is to create a reconstituted wafer. Then, dies are placed on the wafer using a die attach system.
“The problem occurs here. When you build the chips on, the chips are not faultless with respect to each other. It’s very difficult to reserve the chips exactly where they want them within a few microns,” said Tim Olson, chief technology officer of Deca.
That’s where Deca’s Adaptive Patterning technology fits. ASE, an investor in Deca, is producing the M-Series fan-out products based on this patterning technique.
Fig 3: M-Series vs. traditional eWLB fan-out Source: ASE
Deca’s technology consists of a process flow with four modules—wafer prep, panelization, fan-out, and finishing. It enables fan-out packages with multiple layers at 5-5μm with finer RDLs in R&D.
In wafer prep, you plate copper features on the die. Then, in the panelization step, the dies are placed in a reconstituted wafer using a high-speed system at a rate of 28,000 chips per hour. In comparison, a traditional die-attach system operates at 2,000 chips or more an hour.
From there, the actual position of every die is measured on the wafer using an inspection technique. “Die measurement inspection is performed as the eventual step in the panelization process and is used in the real-time design for each panel in manufacturing,” Olson explained.
Then, the RDLs are developed in a chip-first, die-up flow. During the exposure step, the system recalculates the RDL pattern to accommodate every die shift in every wafer. This takes 28 seconds. The overall throughput is 120 wafers an hour.
“Adaptive Patterning is a system designed to automatically compensate for natural variation in manufacturing rather than focusing on elimination of every bit of variation,” Olson said. “In a typical application, devices are allowed to vary by up to 60μm in ‘X’ and ‘Y’ through chip attach, molding and other process steps. Adaptive Patterning removes 97% of the variation automatically through real-time design in manufacturing, enabling efficient interconnect tolerances below 2μm. The next generation of Adaptive Patterning in progress will back 2μm features, with a scaling roadmap to 0.8μm.”
Then, using the same technology from Deca, ASE plans to ramp up panel-level fan-out in 2019 or 2020. ASE’s panel-level fan-out will also utilize Adaptive Patterning.
Meanwhile, Suss MicroTec is developing a dehydrate patterning technology called laser ablation. Suss’ excimer ablation stepper combines ablation with mask-based patterning. It is capable of 3μm line/space with 2-2μm in the works.
“Excimer laser ablation is the direct removal of material using the characteristics of high power UV excimer laser sources. Typical wavelengths are 308nm, 248nm and 193nm,” said Markus Arendt, president and common manager of photonic systems at Suss. “Excimer ablation instantaneously transforms the compatible target material (i.e. polymers, organic dielectrics) from solid phase to gas phase and byproducts (i.e. sub-micron dehydrate carbon particles), resulting in itsy-bitsy to no heat affected zone and much less debris.”
With the tool, Suss is focusing is on wafer-level processes. In addition, it has developed a dual damascene RDL flow with other technologies in R&D.
“The product roadmap includes many recent items,” Arendt said. “However, the two most notable ones are: 1) a recent great field, high-NA projection lens to achieve 2μm L/S in production, and 2) a dual-laser version to allow for a larger scan beam to significantly enlarge throughput and reduce cost-of-ownership.”
Brewer Science, meanwhile, is working on another approach. It uses a thin film in a mold compound that works dote a stencil, which addresses die shift. “It’s a replacement for epoxy mold compound,” said Rama Puligadda, Brewer’s executive director of advanced technologies. “You pre-form a stencil where you want to create cavities in silicon.”
Clearly, there is no shortage of innovative lithographic solutions for packaging. But it will recall some breakthroughs to retreat well beyond 1-1μm. Even if the industry figures it out, it must meet a cost spec for demanding customers. Those factors will reserve the industry sedulous for some time.
More 2.5D/3D, Fan-Out Packages Ahead
Toward High-End Fan-Outs
Fan-Out Wars Begin
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